Power MOSFETs are used in a wide range of applications, including automotive electronics, disk drives, and power supplies. Some low-voltage applications (e.g., less than 30 V) require power MOSFETs to have a low threshold voltage, since the logic level in these applications is low. This is the case in battery switching applications, for example, where the logic level will drop to 1.8 V in the near future.
There are two major factors that affect the threshold voltage in conventional MOSFETs. The first factor is the thickness of the gate oxide. In a MOSFET the threshold voltage is directly proportional to the thickness of the gate oxide. Thus a thinner gate oxide leads to a lower threshold voltage. The second factor is the concentration of the dopant that is implanted or diffused in the body region of the device. In trench-type power MOSFETs, the body region is located in the "mesa" between the trenches. In such a device, the threshold voltage is proportional to the square root of the concentration of dopant in the body region. Thus a lower concentration of dopant in the body region leads to a lower threshold voltage.
There are limits, however, to how thin a gate oxide can be, and how low the concentration of dopant in the body region can be. A gate oxide that is very thin can lead to stability problems at the corners of the trench or reduced reliability of the device. Additionally, a thin gate oxide places a limit on the maximum gate-to-source voltage, V.sub.GS,Max that the device can withstand and increases the gate capacitance, which limits the switching speed of the device. For example, in a device having a gate oxide thickness T.sub.ox of 170 .ANG., the maximum gate voltage is .+-.8 V. Finally, from a manufacturing standpoint, it is very difficult to fabricate a device with a very thin gate oxide layer, especially a gate oxide layer that is less than 100 .ANG. thick.
Similarly, there are limits to how low the concentration of dopant can be in the body region. A very low concentration of dopant in the body region may lead to punchthrough. Punchthrough occurs when the drain voltage is increased to a level where the body region is totally depleted of charge, and therefore the source becomes coupled to the drain. A higher dopant concentration in the body ensures that there will be enough charge in the body region to prevent punchthrough. It is known in the art that, to prevent punchthrough, the charge in the body region of a trench MOSFET must be at least 2.times.10.sup.12 cm.sup.-2, calculated as an integral of the net doping concentration in the body region between the source and drain junctions. A similar restriction applies to the doping of the base region in a bipolar transistor. For silicon bipolar transistors the Gummel number is about 10.sup.12 to 10.sup.13 cm.sup.-2 (see Sze, Physics of Semiconductor Devices, Second Edition, Chapter 3.2.1, page 140).
It is also desirable to have MOSFETs that have a short channel length. This is because the channel length is directly proportional to the on-state resistance of the device, R.sub.DS (on), which should be minimized. Minimizing the channel length leads to a low on-state resistance. At the same time, however, the channel length cannot be made too small. This is because the channel length is defined by the the width of the body region, and the total charge in the body region must remain high enough to prevent punchthrough. Thus, MOSFETs that have short channels must have higher concentrations of dopant present in the body region to prevent punchthrough. The higher concentration of dopant, in turn, leads to a higher threshold voltage. As a result, it is difficult to fabricate a device with a short channel and a low threshold voltage.
In summary, the design of a conventional MOSFET with a low threshold voltage entails a balancing of the following factors: the length of the channel, the total charge in the body region, and the thickness of the gate oxide. The tradeoffs between these factors make it difficult to fabricate a MOSFET with a low threshold voltage and low on-resistance.
An alternative to using a conventional MOSFET for a low threshold device is to use an "accumulation-mode" field-effect transistor, often referred to as an ACCUFET. ACCUFETs are trench-type devices which contain no body region and hence no PN junctions. The "mesa" between the trenched gates is made relatively narrow (e.g., 0.5 to 1.5 .mu.m wide) and the gate material (typically polysilicon) is doped in such a way that it has a work function which forms a depletion region across the entire mesa, much like a junction field-effect transistor (JFET). The current path extends between a source at the top of the mesa and a drain at the bottom of the substrate. The trenches are normally formed in a lightly-doped epitaxial layer which is grown on top of a heavily-doped substrate.
A cross-sectional view of a typical ACCUFET 10 is illustrated in FIG. 1. Trenched gates 11 are etched in a silicon material 12, which includes an N-epitaxial layer 13 grown on an N+ substrate 14. Trenched gates 11 are doped with N-type material and define two cells 10A and 10B. An N+ source 15 is formed at the top of the mesa between gates 11. A metal layer 16 is formed over the source regions, and a power source 17 and a load 18 are connected between the N+ source 15 and the N+ substrate 14, which acts as the drain.
ACCUFET 10 is turned off when the gate voltage is equal to the source voltage (i.e., V.sub.GS =0). For an N-type device, decreasing V.sub.GS results in a strong pinching of the current path so that the leakage current is reduced. In order to achieve this action, the epitaxial layer must be lightly doped (typically below 3.times.10.sup.16 cm.sup.-3) and the channel must be long in comparison with the width of the mesa (typically less than 1.5 .mu.m). If V.sub.GS is increased, the depletion regions surrounding the gates (shown by the dashed lines) contract and open a current path between the source and the drain. With further increasing V.sub.GS the depletion regions continue to contract until eventually accumulation regions are formed adjacent the trenches, enhancing channel conduction and further lowering the on-resistance of the device.
This sequence of events is illustrated in FIGS. 2A, 2B and 2C. FIG. 2A shows ACCUFET 10 in the off condition, FIG. 2B shows ACCUFET 10 turned partially on, and FIG. 2C shows ACCUFET 10 turned fully on, with the accumulation regions being designated by the numeral 19. In FIGS. 2B and 2C, the arrows represent the flow of electrons from the source to the drain. In FIG. 2A, the region 11A near the corner of the trench is where breakdown would occur, possibly causing damage to the gate oxide layer as a result of impact ionization and hot carrier injection into the gate oxide.
Additional information concerning ACCUFETs is given in U.S. Pat. No. 4,903,189 issued to Ngo et al.; B. J. Baliga et al., "The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET", IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pp. 427-429; and T. Syau et al., "Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's", IEEE Electron Device Letters, Vol. 41, No. 5, May 1994, pp. 800-808, each of which is incorporated herein by reference in its entirety.
ACCUFETs can be fabricated with a very high cell density and a very low on-resistance. Despite these advantages, ACCUFETs have not so far achieved widespread use in the field of power semiconductor devices for several reasons. One of the principal reasons is that the leakage current in these devices is typically too high. Conversely, the long channel length and light epitaxial doping concentration required to reduce the leakage current produce a device that has a high on-resistance.
Accordingly, there is a need for a switching device with a low threshold voltage, a thick gate oxide, and low on-resistance.